1. Technical Field
The present invention relates to integrated circuits in general, and in particular to multiport memory cell circuits. Still more particularly, the present invention relates to a multiport memory cell having a reduced number of write wordlines.
2. Description of the Prior Art
Multiport memories are random access memories that have multiple ports to enable parallel accesses, such as simultaneously reading a first memory location via a first port and writing a second memory location via a second port. Typically, multiport memories find their application within integrated circuit devices as register files. A register file is a temporary buffer for storing intermediate results (and arguments) that are produced and used by various functional parts of an integrated circuit device, as is well-known to those skilled in the relevant art.
For an integrated circuit device that includes a register file having a large number of ports, the area occupied by the multiport memory cells within the register file is usually wire-limited. In other words, the large number of wires that are used to access the multiport memory cells within the register file causes the total area to be dependent on the number of wires rather than the number and/or size of transistors used.
For example, if a multiport memory cell has four read ports, 12 write ports, and one write_select port, the multiport memory cell must have 16 wordlines (12 write wordlines and four read wordlines), 16 bitlines (12 write bitlines and four read bitlines), and a write select line. This means there are 17 wires in the wordline direction (12 write wordlines, four read wordlines, and one write_select line) and 16 wires in the bitline direction (12 write bitlines and four read bitlines). The present disclosure provides a solution that reduces the number of wires in the wordline direction of the above-mentioned multiport memory cell to less than 17 wires.